A. Technical Field
The present invention relates to analog-to-digital converters (ADC), and more particularly systems, devices, and methods that provide calibration for multi-stage ADCs.
B. Background of the Invention
Multi-step ADCs are an established architecture for the digitization of analog input signals and are often preferred for high-speed and high-resolution applications. In a pipeline ADC, the task of quantizing the input signal is distributed among multiple stages. Each stage has a sub-ADC that quantizes an input signal, a DAC that subtracts an estimate of the input signal, and a residue amplifier that amplifies the difference to be further processed by a subsequent stage. Together, the DAC and residue amplifier is known as a Multiplying DAC (MDAC). A large number of sub-ADC levels allow a large gain to be used in the first stage, which relaxes the first stage residue amplifier linearity requirements, reduces the number of stages, and suppresses the noise and errors of following stages significantly. In practical implementations, the sub-ADC suffers from static and dynamic inaccuracies that increase the output voltage range over which the residue amplifier must achieve a high level of accuracy. As a result, the practical number of quantization levels that are used in the MDAC is limited.
Traditionally, sub-ADC's in a pipeline ADC are implemented with a FLASH architecture to provide a moderate number of levels with a minimum amount of latency. Static sub-ADC errors in this approach arise from random and systematic comparator offset in the FLASH ADC. Random and systematic errors of the comparator reference voltages, e.g. errors in the reference ladder voltages give rise to similar sub-ADC errors, effectively resulting in additional comparator offset. Increasing the number of sub-ADC bits is desirable for performance reasons, but results in both in an increase in the number of comparators as well as an increase in the matching requirements. To maintain a reasonable amount of area and power consumption without calibration of each comparator's offset, the FLASH sub-ADC resolution is practically limited to about 4-bits. In addition to the static sub-ADC errors, there are also dynamic errors in the first stage's sub-ADC quantization due to timing and bandwidth mismatch between the input sampling of the sub-ADC and the MDAC.
As shown in prior art FIG. 1, a pipeline ADC front-end without a sample-and-hold amplifier (SHA) can save power, but the continuous-time to discrete-time sampling operation is performed onto both the sub-ADC and the MDAC capacitors. At high input frequencies, timing or bandwidth mismatch between the two paths will introduce a dynamic error that adds to the static mismatch error. In multistep or pipeline ADCs, over-range capability of the second and subsequent stages remove the errors caused by the timing and bandwidth mismatches provided the errors are within the over-range boundary. However, as with the FLASH comparator offsets, the timing and bandwidth errors increase the output voltage range of the residue amplifier. It has been shown that this timing and bandwidth error may be calibrated; however, this introduces additional complexity and does not address the static comparator offset.
What is needed are devices, methods and systems to overcome the above-described limitations.